Yield and Performance Enhancement Through Redundancy in VLSI and WSI Multi-Precessor Systems
Author | : Israel Koren |
Publisher | : |
Total Pages | : 52 |
Release | : 1986 |
ISBN-10 | : OCLC:227681588 |
ISBN-13 | : |
Rating | : 4/5 (88 Downloads) |
Book excerpt: New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emergent area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance, and yield improvement techniques. Fault-tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault-tolerance at work in these multi-processor systems. These precepts are useful to then present certain techniques that will incorporate fault-tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques. (Author).