Modelling, Simulation and Architecture Modification of Delta-sigma Fractional-N Frequency Synthesizers
Author | : Zhipeng Ye |
Publisher | : |
Total Pages | : 161 |
Release | : 2008 |
ISBN-10 | : OCLC:795328329 |
ISBN-13 | : |
Rating | : 4/5 (29 Downloads) |
Book excerpt: The wireless communication market has been growing rapidly in recent decades. The frequency synthesizer is a key building block in wireless transceivers. It is used as a local oscillator for frequency translation and channel selection. In this thesis, we provide a brief review of PLL frequency synthesizers. A simulation environment for delta-sigma fractional-N frequency synthesizers is built using Verilog-AMS. The digital delta-sigma modulator is modeled as a finite state machine in order to evaluate how the performance of a frequency synthesizer is affected by the cyclic behavior of the DDSM. In addition, jitter and nonlinearities are considered and added to the model. The spur-minimizing effect of an odd initial condition on the first accumulator of a MASH delta-sigma modulator is demonstrated. A noise reduction technique for a fractional-N frequency synthesizer using a multiphase voltage-controlled oscillator is proposed. We have shown that both in-band and out-of-band phase noise can be reduced by 6 dB for every two-fold increase in the number of phases. The multi-phase VCO is also applied in a dual-loop frequency synthesizer. We show that this dual loop frequency synthesizer achieves a similar power spectrum but with superior frequency resolution compared to a conventional dual-loop frequency synthesizer. We have built an experimental platform based on a Xilinx Virtex-5 FPGA board and have used it to confirm the theoretical analysis and simulations. In order to reduce the hardware consumption of a digital delta-sigma modulator, and consequently the power and area consumption, we propose a reduced complexity architecture which can achieve similar spectral performance compared with a conventional DDSM but with up to 20% lower hardware consumption. We have elaborated a rigorous design methodologies based on this idea of error masking. Individual design strategies are derived for MASH DDSMs and SQ DDSMs, both with and without dither.